Journal

International Journal Papers

  1. Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices,
    Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, Yohei Hori,
    IEICE Transactions on Communications, Vol. E104.B, No. 2, pp.178-186, Feb., 2021.
    DOI: 10.1587/transcom.2020EBP3015
  2. Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping,
    Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike,
    Integration-The VLSI Journal, Elsevier Sciecne BV., Vol.71, pp.144-153, Mar., 2020.
    DOI: 10.1016/j.vlsi.2019.12.002
  3. Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device,
    Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike
    IEICE Transactions on Information and Systems, Vol.E101-D, No.2, pp.303-313, Feb., 2018.
    Copyright@2018 IEICE. (IEEE Transansactions Online top page)
  4. Organic physically unclonable function on flexible substrate operable at 2 V for IoT/IoE security applications,
    Kazunori Kuribara, Yohei Hori, Toshihiro Katashita, Kazuaki Kakita, Yasuhiro Tanaka, Manabu Yoshida,
    Organic Electronics, Vol.51, pp.137-141, Dec., 2017.
  5. Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays,
    Yohei Hori, Toshihiro Katashita, Hyunho Kang, Akashi Satoh, Shinichi Kawamura, and Kazukuni Kobara,
    Journal of Information Processing, Vol.22, No.2, pp.344-356, Apr. 2014.
  6. Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage
    Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
    IEICE Transactions on Electronics, Vol.E95-C, pp.272-279, Apr., 2014.
  7. A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation,
    Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
    IEICE Transactions on Fundamentals, Vol.E96-A, No.12, pp.2533-2541, Dec., 2013.
  8. Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption,
    Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda and Akashi Satoh,
    IEICE Trans. Inf.&Syst. Vol.E96-D, No.11, pp.2333-2343, Nov. 2013. Copyright@2013 IEICE. (IEICE Transactions Online)
  9. A First Report on Electromagnetic and Power Analysis Attacks against 28-nm FPGA Device,
    Yohei Hori, Toshihiro Katashita, Akihiko Sasaki and Akashi Satoh,
    Information - An International Interdisciplinary Journal, Vol.16, No.8(B), pp.5993-6006, 2013.
  10. PUF Evaluation with Post-processing and Modified Modeling Attack,
    Hyunho Kang, Yohei Hori, Toshihiro Katashita, Akashi Satoh, Keiichi Iwamura
    International Journal of Security and Its Applications (IJSIA), Vol.7, No.4, pp.231-241, July, 2013.
  11. A Secure Content Delivery System Based on a Partially Reconfigurable FPGA,
    Y.Hori, H.Yokoyama, H.Sakane and K.Toda,
    IEICE Trans. Inf.&Syst., Vol.E91-D, No.5, pp.1398-1407, 2008. Copyright@2008 IEICE. (IEICE Transactions Online)

Japanese Domestic Journal Papers

  1. Countermeasure against deep learning-based cloning attack on arbiter PUFs by using intentional errors,
    Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama,
    IPSJ Journal, Vol. 61, No. 12, pp.1871-1880, Dec., 2020. (in Japanese)
    DOI: doi/10.20729/00208749
  2. Area and Power Reduction with Dynamic Partial Reconfiguration of Multi-Algorithm Cryptographic Modules,
    Yohei Hori, Hirofumi Sakane, Toshihiro Katashita and Kenji Toda,
    IPSJ Transactions on Computing Systems, Vol.1, No.2, pp.47-58, 2008. (IPSJ Book Park) (in Japanese)
  3. A Novel Test System for Network Filtering Systems on 10 Gigabit Ethernet,
    Toshihiro Katashita, Hirofumi Sakane, Yohei Hori, Kenji Toda,
    IPSJ Journal, Vol.49, No.6, pp.2118-2128, 2008. (in Japanese)
  4. Design and Implementation of FPGA-based Content Protection System,
    Hiroyuki Yokoyama, Yohei Hori, Hirofumi Sakane, Kenji Toda,
    IPSJ Journal, Vol.48, No.9, pp.3253-3265, 2007. (in Japanese)
  5. Implementation of Tsume Shogi Hardware,
    Yohei Hori, Hisanori Saito and Tsutomu Maruyama,
    J.IPSJ, Vol.45, No.3, pp.1014-1031, 2004. (IPSJ Book Park) (in Japanese)

Peer-Reviewed Conference Papers

First-author Conference Papers

  1. A 65-nm SOTB Implementation of a Physically Unclonable Function and Its Performance Improvement by Body Bias Control,
    Yohei Hori, Toshihiro Katashita, and Yasuhiro Ogasahara,
    The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S 2017), San Francisco, CA, U.S., Oct. 16-19, 2017. (Presented on Oct. 18th, 2017)
  2. Energy and Area Saving Effect of Dynamic Partial Reconfiguration on a 28-nm Process FPGA,
    Yohei Hori, Toshihiro Katashita, and Kazukuni Kobara,
    The 2nd IEEE Global Conference on Consumer Electronics (GCCE 2013), Chiba-shi, Chiba, Oct. 1-4, pp.217-218, 2013. (Presented on Oct. 2nd, 2013)
  3. SASEBO-GIII: A Hardware Security Evaluation Board Equipped with a 28-nm FPGA,
    Yohei Hori, Toshihiro Katashita, Akihiko Sasaki and Akashi Satoh,
    The 1st IEEE Global Conference on Consumer Electronics (GCCE 2012), Chiba-shi, Chiba, Japan, Oct. 2-5, pp.666-669, 2012. (Presented on Oct. 5th, 2012)
  4. Electromagnetic Side-channel Attack against 28-nm FPGA Device,
    Yohei Hori, Toshihiro Katashita, Akihiko Sasaki and Akashi Satoh,
    in Pre-proceedings of the 13th International Workshop on Information Security Applications (WISA 2012), Jeju, Korea, Aug. 16-18, 2012. Available from http://isaa.sch.ac.kr/wisa2012/accepted2012.htm. (The pre-proceedings include only a part of the subitted paper.) (Presented on Aug. 16th, 2012)
  5. [Academic Invited Paper] Tackling the Security Issues of FPGA Partial Reconfiguration with Physical Unclonable Functions,
    Yohei Hori, Toshihiro Katashita, and Akashi Satoh,
    The 12th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2012), Las Vegas, Nevada, USA, July 16-17, 2012. pp.79-90. (Presented on July 17, 2012)
  6. Performance Evaluation of Physical Unclonable Functions on 45-nm FPGAs, (in Japanese)
    Yohei Hori, Toshihiro Katashita, Hyunho Kang and Akashi Satoh,
    Multimedia, Distributed, Cooperative and Mobile Symposium (DICOMO'12), Kaga-shi, Ishikawa, Japan, July 4-6, 2012. pp.1928-1933. (Presented on July 6, 2012) (Extended abstract)
  7. Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function,
    Y.Hori, H.Kang, T.Katashita, and A.Satoh,
    7th International Conference on ReConFigurable Computing and FPGAs (ReConFig'11), Cancun, Quintana Roo, Mexico, Nov.30-Dec.2, pp.223-228, 2011. (Presented on Dec. 1, 2011)
  8. Counterfeit LSI detection based on physical property, (in Japanese)
    Yohei Hori, Hyunho Kang, Toshihiro Katashita and Akashi Satoh,
    Multimedia, Distributed, Cooperative and Mobile Symposium (DICOMO'11), Miyazu-shi, Kyoto, Japan, July 6-8, 2011. pp.1296-1300. (Presented on July 8, 2011) (Extended abstract)
  9. Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs,
    Y.Hori, T.Yoshida, T.Katashita, and A.Satoh,
    6th International Conference on ReConFigurable Computing and FPGAs (ReConFig'10), Cancun, Quintana Roo, Mexico, Dec. 13-15, 2010. pp.298-303. (Presented on Dec. 14, 2010.)
  10. Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems,
    Y.Hori, A.Satoh, H.Sakane and K.Toda,
    LNCS 5312, Advances in Information and Computer Security, 3rd International Workshop on Security (IWSEC'08), Takamatsu, Kagawa, Japan, Nov. 25-27, 2008. pp.261-278. (Presented on Nov. 27, 2008.)
  11. Bitstream Encryption and Authentication with AES-GCM in Dynamically Reconfigurable Systems,
    Y.Hori, A.Satoh, H.Sakane and K.Toda,
    18th International Conference on Field-Programmable Logic and Applications (FPL'08), Heidelberg, Germany, Sept. 8-10, 2008. pp.23-28. (Presented on Sept. 8, 2008.)
  12. Area and Power Reduction with Dynamic Partial Reconfiguration of FPGA, (in Japanese),
    Yohei Hori, Hirofumi Sakane, Toshihiro Katashita and Kenji Toda,
    Symposium on Advanced Computing Systems and Infrastructures (SACSIS'08), Tsukuba, Ibaraki, Japan, June 11-13, 2008. pp.307-316.
  13. A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware,
    Y.Hori, H.Yokoyama, H.Sakane and K.Toda,
    6th International Conference on Field-Programmable Technology (ICFPT'07), Kitakyushu, Fukuoka, Japan, Dec. 12-14, 2007. pp.253-256.
  14. Secure Content Distribution System Based on Run-time Partial Hardware Reconfiguration,
    Y. Hori, H. Yokoyama and K. Toda,
    16th International Conference on Field-Programmable Logic and Applications (FPL'06), Madrid, Spain, Aug. 27-29, 2006. pp.637-640.
  15. A Tsume-Shogi Processor Based on Reconfigurable Hardware,
    Y. Hori, T. Maruyama and K. Toda,
    3rd International Conference on Field-Programmable Technology (ICFPT'04), Brisbane, Australia, Dec. 6-8, 2004. pp.347-350.
  16. An FPGA-Based Hardware Platform for Tsume-Shogi, (in Japanese),
    Yohei Hori, Hisanori Saito, and Tsutomu Maruyama,
    8th Game Programming Workshop (GPW'03), Hakone, Kanagawa, Japan, Nov. 7-9, 2003. pp.44-51. (Extended Abstract)
  17. An FPGA-Based Processor for Shogi Mating Problems,
    Y. Hori, M. Sonoyama and T. Maruyama,
    1st International Conference on Field-Programmable Technology (ICFPT'02), Hong-Kong, Hong-Kong, Dec. 16-18, 2002. pp.117-124.
  18. A Shogi Processor with a Field Programmable Gate Array,
    Y.Hori, M.Seki, R.Grimbergen, T.Maruyama and T.Hoshino,
    2nd International Conference on Conmputers and Games (CG 2000), Hamamatsu, Shizuoka, Japan, Oct. 26-28, 2000. pp.297-314.

Co-authored Conference Papers

  1. FPGA implementation of physically unclonable functions based on multi-threshold delay time measurement method to mitigate modeling attacks,
    Tatsuya Ohyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino,
    5th workshop on Artificial Intelligence in Hardware Security (AIHWS), Abu Dhabi, UAE, Mar. 5-8th, 2024. (Presentation by T. Ohyama on Mar. 5th, 2024)
    DOI:
  2. Non-Destructive Hardware Trojan Circuit Screening by Backside Near Infrared Imaging,
    Jun'ichi Sakamoto, Hirofumi Sakane, Yohei Hori, Shin'ichi Kawamura, Yuichi Hayashi, Makoto Nagata,
    IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), Huntsville, Alabama, USA, Oct. 24-26th, 2023. (Presentation by J. Sakamoto on Oct. 25th, 2023)
    DOI: 10.1109/PAINE58317.2023.10317961
  3. Cause Analysis Method of Entropy Loss in Physically Unclonable Function,
    Mitsuru Shiozaki, Yohei Hori, Tatsuya Ohyama, Masayoshi Shirahata, Takeshi Fujino,
    The IEEE International Symposium on Circuits and Systems (ISCAS), Virtual, Oct. 10-21, 2020. pp.598-601. (Presentation by M. Shiozaki on Oct. 12th, 2020)
    DOI: 10.1109/ISCAS45731.2020.9180410
  4. Deep Learning Attack against Large n-XOR PUFs on 180nm Silicon Chips,
    Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama,
    2020 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing (NCSP 2020), Honolulu, Hawaii, USA, Feb. 28 - Mar. 2, 2020. pp.598-601.
  5. A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-based Authentication Scheme,
    Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama,
    International Conference on Information Technology and Communications Security (SecITC 2019), Bucharest, Romania, Nov. 14-15, 2019. pp.65-77 (2020). (Presentation by R. Yashiro on Nov. 14th, 2019)
  6. DeviceVeil: Robust Authentication for Individual USB Devices Using Physical Unclonable Functions,
    Kuniyasu Suzaki, Yohei Hori, Kazukuni Kobara, and Mohammad Mannan,
    The 49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019), Portland, Oregon, June 24-27, 2019 (Presentation by K. Suzaki on June 26th, 2019)
  7. Development of the unified security requirements of PUFs during the standardization process,
    Nicolas Bruneau, Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Soshi Hamaguchi, Yohei Hori, Yousung Kang and Alexander Schaub,
    SecITC 2019, Bucharest, Romania, Nov. 8-9, 2018. (Presentation by N. Bruneau on Nov. 9th, 2018)
  8. Prototype of USB Stick-sized PUF Module for Authentication and Key Generation,
    Toshihiro Katashita, Yohei Hori, and Yasuhiro Ogasahara,
    IEEE Global Conference on Consumer Electronics (IEEE GCCE 2017), Nagoya, Aichi, Oct. 24-27, 2017. (Presentation at Demo Session by T. Katashita and Y. Hori on Oct. 26th, 2017)
  9. Implementation of Pseudo Linear Feedback Shift Register Physical Unclonable Function on Silicon,
    Yasuhiro Ogasahara, Yohei Hori, and Hanpei Koike,
    IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, Canada, May 22-25, 2016. (Presentation by Y. Ogasahara on May 23rd, 2016)
  10. Robust and Compact Key Generator Using Physically Unclonable Function Based on Logic-Transistor-Compatible Poly-Crystalline-Si Channel FinFET Technology,
    S. O'uchi, Y. Liu, Y. Hori, T. Irisawa, H. Fuketa, T. Mori, Y. Morita, T. Nakagawa, J. Tsukada, H. Koike, M. Masahara, and T. Matsukawa,
    IEEE International Electron Devices Meeting (IEDM 2015), Washington, DC, USA, December 7-9, 2015. (Presentation by S. O'uchi on Dec. 9th, 2015)
  11. Standard Cell Implementation of Buskeeper PUF with Symmetric Inverters and Neighboring Cells for Passing Randomness Tests,
    Yasuhiro Ogasahara, Yohei Hori, and Hanpei Koike,
    IEEE Global Conference on Consumer Electronics (GCCE 2015), Osaka, Japan, October 27-30, 2015. (Presentation by Ogasahara on October 30th, 2015)
  12. Experimental study of variability in polycrystalline and crystalline silicon channel FinFET CMOS inverters,
    Liu, Y. X., Hori, Y., Ohno, M., Matsukawa, T., Endo, K., O'uchi, S., and Masahara, M.,
    IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA 2015), Hsinchu, Taiwan, April 27-29, 2015. pp.1-2. (Presentation by Liu on Apr. 29th, 2015)
  13. Correlation Power Analysis using Bit-Level Biased Activity Plaintexts against AES Cores with Countermeasures,
    Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Le, Hanh-Ha, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
    IEEE International Symposium on Electromagnetic Compatibility (EMC 2014), Tokyo, Japan, May 12-16, 2014. pp.306-309. (Presentation by Fujimoto on May 14th, 2014)
  14. Cryptographic Key Generation from PUF Data Using Efficient Fuzzy Extractors,
    Hyunho Kang, Yohei Hori, Toshihiro Katashita, Manabu Hagiwara, Keiichi Iwamura
    The 16th International Conference on Advanced Communications Technology (ICACT 2014), Pyeongchang, Korea, February 16-19, 2014, pp.23-26, 2014. (Presentation by Kang on Feb. 17th, 2014)
  15. Performance Analysis for PUF Data Using Fuzzy Extractor,
    Hyunho Kang, Yohei Hori, Toshihiro Katashita, Manabu Hagiwara, Keiichi Iwamura
    The 8th International Conference on Ubiquitous Information Technologies and Applications (CUTE 2013), Danang, Vietnam, December 18-20, Lecture Note in Electrical Engineering, Vol. 280, pp.277-284, 2014. (Presentation by Kang on Dec. 18th, 2013)
  16. A Novel Smart Card Development Platform for Evaluating Physical Attacks and PUFs,
    Toshihiro Katashita, Akihiko Sasaki, and Yohei Hori,
    The 2nd IEEE Global Conference on Consumer Electronics (GCCE2013), pp.37-39, 2013. (Poster presentation by Katashita and Hori on Oct. 2nd, 2013)
  17. On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel Analysis,
    Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger
    The 12th International Symposium on Electromagnetic Compatibility (EMC EUROPE 2013), September 2nd-6th, Brugge, Belgium, pp.405-410, 2013. (Presentation by Fujinoto on September 4th, 2013)
  18. Towards Efficient Evaluation of EM Information Leakage from Cryptographic Devices,
    Naofumi Homma, Yu-ichi Hayashi, Toshihiro Katashita, Yohei Hori, Takafumi Aoki,
    The 22nd International Workshop on Post-Binary ULSI Systems (ULSIWS), pp.50-55, 2013. (Presentation by Homma on May 20th, 2013)
  19. Performance of Physical Unclonable Functions with Shift-Register-Based Post-Processing,
    Hyunho Kang, Yohei Hori, Toshihiro Katashita, Akashi Satoh,
    International Conference on Security Technology (SecTech 2012), pp.14-21, 2012. (Presentation by Kang on Nov. 29th, 2012)
  20. Development of Evaluation Environment for Physical Attacks against Embedded Devices,
    Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Mitsuru Shiozaki and Takeshi Fujino,
    The 1st IEEE Global Conference on Consumer Electronics (GCCE2012), pp.598-601, 2012. (Presentation by Katashita on Oct. 4th, 2012)
  21. Performance Evaluation of the First Commercial PUF-embedded RFID,
    Hyunho Kang, Yohei Hori and Akashi Satoh,
    The 1st IEEE Global Conference on Consumer Electronics (GCCE2012), pp.5-8, 2012. (Presentation by Kang on Oct. 2nd, 2012)
  22. Measurement of side-channel information from cryptographic devices on security evaluation platform: Demonstration of SPACES project,
    Sho Endo, Naofumi Homma, Takafumi Aoki, Toshihiro Katashita, Yohei Hori, Kazuo Sakiyama, Makoto Nagata, Jean-Luc Danger, Thanh-Ha Le, Pirouz Bazargan
    The Society of Instrument and Control Engineers (SICE) Annual Conference, pp.313-316, 2012. (Presentation by Endo on Aug. 21st, 2012)
  23. PUF Evaluation against Linear Programming Model on SASEBO-GII,
    Hyunho Kang, Yohei Hori, Toshihiro Katashita and Akashi Satoh,
    (DICOMO2012), Kaga, Ishikawa, July 4-6, 2012. pp.1947-1950. (Presentation by Kang, July 6th, 2012) (Extended abstract review)
  24. Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing,
    Toshihiro Katashita, Yohei Hori, Hirofumi Sakane and Akashi Satoh,
    Non-Invasive Attack Testing Workshop (NIAT 2011), Sep. 2011. Nara, Japan. (Presentation by Katashita on Sep. 27th, 2011)
  25. A Fast Power Current Analysis Methodology using Capacitor Charging Model for Side Channel Attack Evaluation,
    Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Hirofumi Sakane and Akashi Satoh,
    International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2011, poster, no review process), Sep. 2011. Nara, Japan. (Presentation by Fujimoto on Sep. 30th, 2011)
  26. Development of a side-channel standard evaluation board for IC cards,
    Toshihiro Katashita, Yohei Hori, Akashi Satoh,
    DICOMO 2011, pp.1301-1307, 2011. (Presentation by Katashita on July 7th, 2011)
  27. A Fast Power Current Analysis Methodology Using Capacitor Charging Model for Side Channel Attack Evaluation,
    Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, and Akashi Satoh,
    The 4th IEEE Intl. Symp. Hardware-Oriented Security and Trust (HOST 2011), P35, pp. 87-92, June 2011. San Diego. (Presentation by Fujimoto on June 5th, 2011)

Talks

Invited Talks

  1. Basics, Applications and International Standardization of Physically Unclonable Functions (PUFs),
    IEICE RECONF Workshop, virtual workshop, 8th June, 2021.
  2. Physically Unclonable Function (PUF) for anti-counterfeiting,
    International Symposium on Anti-counterfeiting II, JIPDEC, Tokyo, 7th December, 2012. (Coauthored with Akashi Satoh)
  3. The latest side-channel attack countermeasures and the trend of security standardization,,
    Information Security Seminar, Industrial Technology Center of Okayama Prefecture, Okayama, 14th November, 2012.
  4. SASEBO Project -Past, Now and Future,
    Lecture Meeting on Hardware Security, National Security Research Institute (NSRI), Daejeon, Korea, 19th September, 2012.
  5. Tackling the Security Issues of FPGA Partial Reconfiguration with Physical Unclonable Functions,
    The 12th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA2012), 17 July, 2012.
  6. The Latest Design Method of Dynamically Reconfigurable Systems and Their Security,
    Japan Consortium for the Reconfigurable-Hardware Next Generation (JACORN2010), 17 Sept., 2010.

Requested Talks

  1. Standardization of Physically Unclonable Function and its application to IC chip security,
    IMPULSE Consortium, 4th seminar 2022fy, online, 22nd Feb., 2023.
  2. Basics, applications and internatioanl standardization of Physically Unclonable Function (PUF),
    The Japan Institute of Electronics Packaging (JIEP) Artificial Intelligence and IoT (AI2oT) seminar, virtual seminar, 3rd Aug., 2022.
  3. Physically Unclonable Function (PUF) as a Root of Trust,
    26th AI Chip Design Center Forum, Online, 27th Aug., 2021.
  4. Basics, applications, standardization of Physically Unclonable Function (PUF),
    FY2020 NEDO IoT School, virtual seminer, 9th February, 2021.
  5. Hardware security research in AIST: Research trend and standardization of Physically Unclonable Function (PUF),
    Security meeting, ICSS-RT, virtual meeting, 16th December, 2020.
  6. Research trend and standardization of Physically Unclonable Function (PUF),
    Hardware Security Forum 2019，Asakusabashi Hulic Conference, 6th December, 2019.
  7. Fundamentals, applications, and standardization of Physically Unclonable Functions (PUFs),
    NEDO IoT FY2018 2nd HRD Seminar, Waseda University, 8th January, 2019.
  8. Introduction to Physically Unclonable Function and Its Application to IoT Security,
    The 36th Information Security Seminar, Bank of Japan, 11th December, 2017.
  9. Basics and trend of PUFs,
    Japan Electronics and Information Technology Industries Association (JEITA), 19th September, 2017.
  10. Physically Unclonable Function (PUF) and its applications,
    IEICE Society Conference, Tokyo City University, 15th September, 2017.
  11. Challenges in Hardware Security,
    Institute of Information Security, 28th October, 2016.
  12. Highly dependable systems using reconfigurable systems,,
    Lecture Meeting on Hardware Security, National Security Research Institute (NSRI), Daejeon, Korea, 20th September, 2012.
  13. On the side-channel attacks and physical unclonable functions,
    Lecture Meeting on Hardware Security, National Security Research Institute (NSRI), Daejeon, Korea, 20th September, 2012.
  14. Side-channel attack evaluation of AES implementations on SASEBO-GIII,
    Joint Workshop on Cryptographic Algorithm and its Applications (JWCAA 2012), IPA, Tokyo, 13th Aug., 2012.
  15. Applications of reconfigurable devices and their security,
    Lecture at Kanazawa Institute of Technology, 11 Nov., 2011.
  16. The Future Brought by Flexible Hardware,
    Project seminar at Kumamoto University, 19 Mar., 2010.
  17. How to Use Partial Reconfiguration of FPGA,
    17th FPGA/CPLD Design Conference, Pacifico Yokohama, 29 Jan., 2010.
  18. FPGA Dynamic Partial Reconfiguration and its Applications,
    Embedded Technology 2009, Pacifico Yokohama, 19 Nov., 2009.
  19. Trends and Applications of Dynamic Partial Reconfiguration of FPGAs,
    15th FPGA/CPLD Design Conference, Pacifico Yokohama, 24 Jan., 2008.
  20. A secure content delivery system based on partial reconfiguration of an FPGA,
    Forum on Information Technology (FIT'07), Chukyo University, 7 Sept., 2007.

Seminar

  1. Multi-functional, high-performance and high-reliability systems Using Dynamic Partial Reconfiguration of FPGAs,
    Nihon Techno Center, 6-7 Feb., 2008.

Books and Commercial Magazines

Articles in Commercial Books and Magazines

  1. Malicious Attacks on Electronic Systems and VLSIs for Security,
    Takeshi Fujino, Daisuke Suzuki, Yohei Hori, Mitsuru Shiozaki, Masaya Yoshikawa, Toshiya Asai, Masayoshi Yoshimura
    in "VLSI Design and Test for Systems Dependability", Chap.10, pp.395-437, 2019. (eBook 2018)
    (My parts are 10.2 "Methods for Tampering CryptographicVLSIs" and 10.6 "Evaluation of Tamper Resistance of VLSIs")
  2. Power analysis of cryptography on microprocessors (Part 2)---Side-channel attack on AES-128 and its countermeasures,
    Toshihiro Katashita, Yohei Hori,
    Interface, CQ Publishing Co., Ltd., Oct. 2013. pp.130-136.
  3. Power analysis of cryptography on microprocessors (Part 1)---The principle of power analysis,
    Yohei Hori, Toshihiro Katashita,
    Interface, CQ Publishing Co., Ltd., Sept. 2013. pp.122-130.
  4. Partial Reconfiguration of FPGAs,
    Yohei Hori, Hiroyuki Kawai, and Yoshiki Yamaguchi,
    Design Wave Magazine, CQ publishing, Sept. 2007. pp.129-135.
  5. A tsume-shogi processor with a Field-Programmable Gate Array,
    Yohei Hori, Rijer Grimbergen, and Tsutomu Maruyama,
    Progress in Computer Shogi 4, Chapter 3, Hitoshi Matsubara (Ed.), Kyoritsu Shuppan, 2003. pp.41--67.

Patents

Coming soon...

Papers without peer review

1st-Author Domestic Workshop Papers

  1. FPGA Implementation of a Cipher Key Generation Circuit Using PUF and Fuzzy Extractor on SASEBO-G3,
    Yohei Hori, Toshihiro Katashita
    IEICE Technical Report, RECONF2015-19, Vol.115, No.109, Vol.115, pp.103-108, 2015. (presentation: June 20, 2015)
  2. Performance Evaluation of Physical Unclonable Functions on Kintex-7 FPGA,
    Yohei Hori, Toshihiro Katashita, Kazukuni Kobara,
    IEICE Technical Report, RECONF2013-17, pp.91-96, 2013.
  3. Power Consumption Evaluation of Dynamically Reconfigurable Multi-cryptoprocessor on Virtex-5 FPGA,
    Yohei Hori, Toshihiro Katashita and Akashi Satoh,
    IEICE Technical Report, Vol.111, No.31, RECONF2011-17, pp.97-102, 2011.
  4. Electromagnetic Analysis against AES on SASEBO-GII,
    Yohei Hori, Toshihiro Katashita, and Akashi Satoh,
    Symposium on Cryptography and Information Security (SCIS2011), 2011.
  5. Quantitative Evaluation of Arbiter PUFs on FPGA,
    Yohei Hori, Takahiro Yoshida, Toshihiro Katashita and Akashi Satoh,
    IEICE Technical Report, Vol.110, No.204, RECONF2010-37, pp.115-120, 2010.
  6. Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis,
    Yohei Hori, Mai Itoh and Hideki Imai,
    IEICE Technical Report, Vol.109, No.26, RECONF2009-12, pp.67-72, 2009.
  7. Development of Side-channel Attack Standard Evaluation BOard and Tool,
    Yohei Hori, Toshihiro KATASHITA, Hirofumi SAKANE, Akashi SATOH, Kenji TODA, and Hideki IMAI,
    IEICE Technical Report, Vol.108, No.300, RECONF2008-54, pp.87-92, 2008.
  8. Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems,
    Yohei Hori, Akashi Satoh, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.108, No.48, RECONF2008-3, pp.13-18, 2008.
  9. A Study of the Effectiveness of Dynamic Partial Reconfiguration for Size and Power Reduction,
    Yohei Hori, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.107, No.418, RECONF2007-56, pp.31--36, 2008.
  10. Secure Content Delivery System with Self Run-time Partial Reconfiguration of FPGA,
    Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.106, No.602, CPSY2006-86, pp.7--12, 2007.
  11. Design and Implementation of Self Run-time Partial Reconfiguration System,
    Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.106, No.458, RECONF2006-75, pp.61-68, 2007.
  12. Approaches to Improving Performance of ART-Linux with Dedicated Hardware,
    Yohei Hori, Toshio Nakajima, Toshihiro Katashita, Mamoru Sekiyama, and Kenji Toda,
    IEICE Technical Report, CPSY2004-108, pp.19--24, 2005.

Co-Authored Domestic Workshop Papers

Omitted

First-Author Discussion Papers

  1. High-speed computation of shogi mating problems with FPGA,
    Yohei Hori, Tsutomu Maruyama, and Tsutomu Hoshino,
    62nd IPSJ National Convention, 2001.
  2. High-speed computation of shogi mating problems with FPGA -- piece cover,
    Yohei Hori, Minenobu Seki, Tsutomu Maruyama and Tsutomu Hoshino,
    60th IPSJ National Convention, 2000.

Co-Authored Discussion Papers

Omitted

Other Articles

  1. Physically Unclonable Function (PUF) and Its Applications
    Yohei Hori,
    in Special Section " Challenges and Perspectives on Hardware Security," The Journal of the Institute of Electronics, Information and Communications Engineerings, Vol.103, No.1, Jan., 2020. pp.57-61.
  2. A Compact and Low-power Multi-crypto Processor Using Dynamic Partial Reconfiguration of FPGA,
    Yohei Hori,
    Tokyo Electron Device (TED) Web site, 2009.
  3. Cutting edge of reconfigurable systems research, Chapter 3, Research trends,
    Yohei Hori,
    IEICE Information Systems Society, Vol.12, No.4, Feb., 2008. pp.8-9.