First Author Publications

Journal

  1. Area and Power Reduction with Dynamic Partial Reconfiguration of Multi-Algorithm Cryptographic Modules, (in Japanese),
    Yohei Hori, Hirofumi Sakane, Toshihiro Katashita and Kenji Toda,
    IPSJ Transactions on Computing Systems, Vol.1, No.2, pp.47-58, 2008. (IPSJ Book Park)
  2. A Secure Content Delivery System Based on a Partially Reconfigurable FPGA,
    Y.Hori, H.Yokoyama, H.Sakane and K.Toda,
    IEICE Trans. INF.&SYST., Vol.E91-D, No.5, pp.1398-1407, 2008. (IEICE Transactions Online)
  3. Implementation of Tsume Shogi Hardware, (in Japanese),
    Yohei Hori, Hisanori Saito and Tsutomu Maruyama,
    J.IPSJ, Vol.45, No.3, pp.1014-1031, 2004. (IPSJ Book Park)

Peer-Reviewed Conference Papers

  1. Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function,
    Y.Hori, H.Kang, T.Katashita, and A.Satoh,
    7th International Conference on ReConFigurable Computing and FPGAs (ReConFig'11), Cancun, Quintana Roo, Mexico, Nov.30-Dec.2, pp.223-228, 2011. (Presentation: Dec. 1, 2011)
  2. Counterfeit LSI detection based on physical property, (in Japanese)
    Yohei Hori, Hyunho Kang, Toshihiro Katashita and Akashi Satoh,
    Multimedia, Distributed, Cooperative and Mobile Symposium (DICOMO'11), Miyazu-shi, Kyoto, July 6-8, 2011. pp.1296-1300. (Presentation: July 8, 2011)
  3. Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs,
    Y.Hori, T.Yoshida, T.Katashita, and A.Satoh,
    6th International Conference on ReConFigurable Computing and FPGAs (ReConFig'10), Cancun, Quintana Roo, Mexico, Dec. 13-15, 2010. pp.298-303. (Presentation: Dec. 14, 2010.)
  4. Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems,
    Y.Hori, A.Satoh, H.Sakane and K.Toda,
    LNCS 5312, Advances in Information and Computer Security, 3rd International Workshop on Security (IWSEC'08), Takamatsu, Kagawa, Japan, Nov. 25-27, 2008. pp.261-278. (Presentation: Nov. 27, 2008.)
  5. Bitstream Encryption and Authentication with AES-GCM in Dynamically Reconfigurable Systems,
    Y.Hori, A.Satoh, H.Sakane and K.Toda,
    18th International Conference on Field-Programmable Logic and Applications (FPL'08), Heidelberg, Germany, Sept. 8-10, 2008. pp.23-28. (Presentation: Sept. 8, 2008.)
  6. Area and Power Reduction with Dynamic Partial Reconfiguration of FPGA, (in Japanese),
    Yohei Hori, Hirofumi Sakane, Toshihiro Katashita and Kenji Toda,
    Symposium on Advanced Computing Systems and Infrastructures (SACSIS'08), Tsukuba, Ibaraki, Japan, June 11-13, 2008. pp.307-316.
  7. A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware,
    Y.Hori, H.Yokoyama, H.Sakane and K.Toda,
    6th International Conference on Field-Programmable Technology (ICFPT'07), Kitakyushu, Fukuoka, Japan, Dec. 12-14, 2007. pp.253-256.
  8. Secure Content Distribution System Based on Run-time Partial Hardware Reconfiguration,
    Y. Hori, H. Yokoyama and K. Toda,
    16th International Conference on Field-Programmable Logic and Applications (FPL'06), Madrid, Spain, Aug. 27-29, 2006. pp.637-640.
  9. A Tsume-Shogi Processor Based on Reconfigurable Hardware,
    Y. Hori, T. Maruyama and K. Toda,
    3rd International Conference on Field-Programmable Technology (ICFPT'04), Brisbane, Australia, Dec. 6-8, 2004. pp.347-350.
  10. An FPGA-Based Hardware Platform for Tsume-Shogi, (in Japanese),
    Yohei Hori, Hisanori Saito, and Tsutomu Maruyama,
    8th Game Programming Workshop (GPW'03), Hakone, Kanagawa, Japan, Nov. 7-9, 2003. pp.44-51. (Exteded Abstract)
  11. An FPGA-Based Processor for Shogi Mating Problems,
    Y. Hori, M. Sonoyama and T. Maruyama,
    1st International Conference on Field-Programmable Technology (ICFPT'02), Hong-Kong, Hong-Kong, Dec. 16-18, 2002. pp.117-124.
  12. A Shogi Processor with a Field Programmable Gate Array,
    Y.Hori, M.Seki, R.Grimbergen, T.Maruyama and T.Hoshino,
    2nd International Conference on Conmputers and Games (CG 2000), Hamamatsu, Shizuoka, Japan, Oct. 26-28, 2000. pp.297-314.

Domestic Workshop (Non-reviewed papers)

  1. Power Consumption Evaluation of Dynamically Reconfigurable Multi-cryptoprocessor on Virtex-5 FPGA,
    Yohei Hori, Toshihiro Katashita and Akashi Satoh,
    IEICE Technical Report, Vol.111, No.31, RECONF2011-17, pp.97-102, 2011.
  2. Electromagnetic Analysis against AES on SASEBO-GII，
    Yohei Hori，Toshihiro Katashita, and Akashi Satoh,
    Symposium on Cryptography and Information Security (SCIS2011)， 2011.
  3. Quantitative Evaluation of Arbiter PUFs on FPGA,
    Yohei Hori, Takahiro Yoshida, Toshihiro Katashita and Akashi Satoh,
    IEICE Technical Report, Vol.110, No.204, RECONF2010-37, pp.115-120, 2010.
  4. Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis,
    Yohei Hori, Mai Itoh and Hideki Imai,
    IEICE Technical Report, Vol.109, No.26, RECONF2009-12, pp.67-72, 2009.
  5. Development of Side-channel Attack Standard Evaluation BOard and Tool,
    Yohei Hori, Toshihiro KATASHITA, Hirofumi SAKANE, Akashi SATOH, Kenji TODA, and Hideki IMAI,
    IEICE Technical Report, Vol.108, No.300, RECONF2008-54, pp.87-92, 2008.
  6. Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems,
    Yohei Hori, Akashi Satoh, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.108, No.48, RECONF2008-3, pp.13-18, 2008.
  7. A Study of the Effectiveness of Dynamic Partial Reconfiguration for Size and Power Reduction,
    Yohei Hori, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.107, No.418, RECONF2007-56, pp.31--36, 2008.
  8. Secure Content Delivery System with Self Run-time Partial Reconfiguration of FPGA,
    Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.106, No.602, CPSY2006-86, pp.7--12, 2007.
  9. Design and Implementation of Self Run-time Partial Reconfiguration System,
    Yohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, and Kenji Toda,
    IEICE Technical Report, Vol.106, No.458, RECONF2006-75, pp.61-68, 2007.
  10. Approaches to Improving Performance of ART-Linux with Dedicated Hardware,
    Yohei Hori, Toshio Nakajima, Toshihiro Katashita, Mamoru Sekiyama, and Kenji Toda,
    IEICE Technical Report, CPSY2004-108, pp.19--24, 2005.

Discussion Papers (Non-reviewed papers)

  1. High-speed computation of shogi mating problems with FPGA,
    Yohei Hori, Tsutomu Maruyama, and Tsutomu Hoshino,
    62nd IPSJ National Convention, 2001.
  2. High-speed computation of shogi mating problems with FPGA -- piece cover,
    Yohei Hori, Minenobu Seki, Tsutomu Maruyama and Tsutomu Hoshino,
    60th IPSJ National Convention, 2000.

Articles in Commercial Books and Magazines

  1. Partial Reconfiguration of FPGAs,
    Yohei Hori, Hiroyuki Kawai, and Yoshiki Yamaguchi,
    Design Wave Magazine, CQ publishing, Sept. 2007. pp.129-135.
  2. A tsume-shogi processor with a Field-Programmable Gate Array,
    Yohei Hori, Rijer Grimbergen, and Tsutomu Maruyama,
    Progress in Computer Shogi 4, Chapter 3, Hitoshi Matsubara (Ed.), Kyoritsu Shuppan, 2003. pp.41--67.

Other Articles

  1. A Compact and Low-power Multi-crypto Processor Using Dynamic Partial Reconfiguration of FPGA,
    Yohei Hori,
    Tokyo Electron Device (TED) Web site, 2009.
  2. Cutting edge of reconfigurable systems research, Chapter 3, Research trends,
    Yohei Hori,
    IEICE Information Systems Society, Vol.12, No.4, Feb., 2008. pp.8-9.

Talks

Invited Talks

  1. The Latest Design Method of Dynamically Reconfigurable Systems and Their Security,
    JACORN2010, 17 Sept., 2010.

Requested Talks

  1. Applications of reconfigurable devices and their security,
    Lecture at Kanazawa Institute of Technology, 11 Nov., 2011.
  2. The Future Brought by Flexible Hardware,
    Project seminar at Kumamoto University, 19 Mar., 2010.
  3. How to Use Partial Reconfiguration of FPGA,
    17th FPGA/CPLD Design Conference, Pacifico Yokohama, 29 Jan., 2010.
  4. FPGA Dynamic Partial Reconfiguration and its Applications,
    Embedded Technology 2009, Pacifico Yokohama, 19 Nov., 2009.
  5. Trends and Applications of Dynamic Partial Reconfiguration of FPGAs,
    15th FPGA/CPLD Design Conference, Pacifico Yokohama, 24 Jan., 2008.
  6. A secure content delivery system based on partial reconfiguration of an FPGA,
    Forum on Information Technology (FIT'07), Chukyo University, 7 Sept., 2007.

Seminar

  1. Multi-functional, high-performance and high-reliability systems Using Dynamic Partial Reconfiguration of FPGAs,
    Nihon Techno Center, 6-7 Feb., 2008.

Patents

Coming soon...

Co-author Publications

Omitted