Personal Information

Name:
Yohei HORI, Ph.D.
Affiliation:
Integrated Circuit Design Research Team,
Semiconductor Frontier Research Center (SFRC),
National Institute of Advanced Industrial Science and Technology (AIST)
Contact:

Research and Professional Experience

Oct. 2023 - present
Senior Researcher at
Semiconductor Frontier Research Center (SFRC), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
June 2021 - present
Senior Researcher at
(Concurrently work for) AI Chip Design Open Innovation Laboratory (AIDL), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Nov. 2018 - present
Senior Researcher at
(Concurrently work for) Cyber Physical Security Research Center (CPSEC), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
May 2022 - Apr. 2023
Planning Officer at
Research Strategy Planning Department (researchstrapd), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Apr. 2020 - Mar. 2024
Senior Researcher at
Device Technology Research Institute (D-Tech), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Apr.2015 - Mar.2020
Senior Researcher at
Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Apr.2012 - Mar.2015
Researcher at
Research Institute for Secure Systems (RISEC), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Apr.2010 - Mar.2012
Research scientist at
Research Center for Information Security (RCIS), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Apr.2010 - Mar.2012
Visiting assistant professor at
Research and Development Initiative, Chuo University, Japan.
Nov.2008 - Mar.2010
Research scientist and assistant professor at
Research and Development Initiative, Chuo University, Japan.
July 2005 - Nov.2008
Post-doctoral researcher at
Information Technology Research Institute (ITRI), National Institute of Advanced Industrial Science and Technology (AIST), Japan.
Apr.2004 - June 2005
Post-doctoral researcher at
Information Processing Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Japan.

Education

Apr.1999 - Mar.2004
Doctoral Program in Functioning Systems, Graduate School of Engineering, University of Tsukuba, Japan.
Ph.D. (Engineering)
Apr.1995 - Mar.1999
Department of Engineering Systems, Third Cluster, University of Tsukuba, Japan
Apr.1992 - Mar.1995
Niigata Prefectural Takada High School, Japan

Academic Activity

  • Member of the Information Processing Society of Japan (IPSJ)
  • Member of the Institute of Electronics, Information and Communication Engineerings (IEICE), Japan.
  • Member of the Institute of Electrical and Electronics Engineers (IEEE).
2012 - 2018.5
Committee, Reconfigurable Systems (RECONF) Tech. Committee, IEICE.
2012 - 2013
Editorial Board, Special Session on Reconfigurable Systems, IEICE Transactions on Information and Systems.
2012 - 2012
Program Committee, 3rd International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEAT2012)
2011 - 2012
Organizational Committee and Program Committee, Symposium on Advanced Computing Systems and Infrastructures (SACSIS2012)
2011
Program Committee, 2nd International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEAT2011)
2011
Editorial Board, Special Session on Reconfigurable Systems, IEICE Transactions on Information and Systems.
2010.12
Poster Chair and Organizational Committee, 13th International Workshop on Cryptographic Hardware and Embedded Systems (CHES2011)
2010.7
Organizational Committee and Program Committee, Symposium on Advanced Computing Systems and Infrastructures (SACSIS2011)
2010
Program Committee, 1st International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEAT2010)
2009.5 - present
Secretory of Reconfigurable Systems Research Group (RECONF), IEICE, Japan.
2008.9
Editorial Board, Special Session on Reconfigurable Systems, IEICE Transactions on Information and Systems.
2007.5-2009.5
Assistant secretory of Reconfigurable Systems Research Group (RECONF), IEICE, Japan.

Award

Oct 26, 2017
IEEE GCCE 2017 Excellent Demo! Award (2nd Prise), IEEE GCCE 2017
Toshihiro Katashita, Yohei Hori, Yasuhiro Ogasahara
"Prototype of USB Stick-sized PUF Module for Authentication and Key Generation"
Apr. 15, 2014
JIP Specially Selected Paper, IPSJ Journal of Information Processing (JIP)
Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shinichi Kawamura, and Kazukuni Kobara
"Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays"
Feb. 17, 2014
Outstanding Paper Award, ICACT2014
Hyunho Kang, Yohei Hori, Toshihiro Katashita, Manabu Hagiwara, and Keiichi Iwamura
"Cryptographic Key Generation from PUF Data Using Efficient Fuzzy Extractors"
Oct. 3, 2013
Outstanding Poster Award, IEEE GCCE2013
Toshihiro Katashita, Akihiko Sasaki, and Yohei Hori,
"A Novel Smart Card Development Platform for Evaluating Physical Attacks and PUFs"
Oct. 4, 2012
Excellent Paper Award, IEEE GCCE2012
Hyunho Kang, Yohei Hori, Akashi Satoh,
"Performance Evaluation of the First Commercial PUF-embedded RFID"
Aug. 30, 2012
Paper Award, DICOMO2012
Yohei Hori, Toshihiro Katashita, Hyunho Kang, Akashi Satoh,
"Performance Evaluation of Physical Unclonable Functions on 45-nm FPGAs"
July 6, 2012
Presentation Award, DICOMO2012
Yohei Hori,
"Performance Evaluation of Physical Unclonable Functions on 45-nm FPGAs"
Nov. 19, 2008
Design Gaia Poster Award, Design Gaia 2008
Yohei Hori,
"Development of Side-channel Attack Standard Evaluation BOard and Tool"