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Fabrication technology of Si nanowire waveguides by electron-beam (EB) lithography


This page describes simple tips for fabrication of Si nanowire waveguides for technology I have developed. It is very simple and fast-to-fabricate technology. The loss of waveguides is very small, it is hard to measure and it is not noticeable for 3-mm-long waveguide. There is a good butt fiber coupling. The total optical loss for fiber-waveguide-fiber coupling is low and it is about 8-9 dB. The variation of fiber-to-fiber loss between different waveguides fabricated on the same wafer is less than 0.1 dB.

This is a simple and fast-to-fabricate technology, which allows to obtain practically lossless waveguide with efficient fiber-to-waveguide loss with minimum efforts. For me only one or two days from a design to full fabrication and measurement of a sample with Si nano-wire waveguides.

I did not see a difference for fiber-waveguide-fiber transmission between a straight waveguide (length ~3.5 mm) and snake-shape waveguide (length ~ 7 mm). Since for my transmission-evaluation setup (See here), the difference of the transmission between similar waveguides on the same sample does not exceed 0.1-0.2 dB, the loss of Si nanowire waveguides is negligible small (at least smaller than 0.5 dB/cm).

Technology flow:

Straight Si nanowire waveguide with spot-size converters at both sides.

See examples .J01 files in

In my case the length is 3.5 mm. The modulation-modulated exposure is important. The border area of higher EB exposure shown in red and main area of smallest exposure shown in yellow color.

1) I buy 6" wafer from SoiTech, Si thickness is 220 nm, SiO2 box thickness 3 um (1 um and thinner is also fine).

Also, I have tried aSi CVD-deposited on SiO2/Si. The aSi nanowaveguides shows a small loss.

However, mainly I use Soitech wafer foe a simple reason that I have many Soitech wafers, but aSi should be fabricated.

2) I dice the wafer into 20mm x 20 mm samples, following by a cleaning of the surface

3) Sputtering: SiO2 (50 nm)+ Cr(5 nm)+ Au(70 nm)+Cr(5 nm)

4) g-line stepper lithography (reticle 10, Field mark see here)

5) Ar milling untill ~10 nm of SiO2 is removed

These first 5 steps I do about once per year for about 100 samples at once.

6) EB lithography.

negative chemically-enhanced EB resist (exposed areas remains after developing). Thickness of EB resist is about 250 nm thick. HDMS is used for better adhision. Beam current is 400 pA.

Important: the modulated-exposure method should be used for EB writing. It allows to obtain a rectangular shape of EB resist.

7) ICP-RIE etching

8) wet etching (optional)

9) removal of SiO2 mask in diluted BHF or HF

10) PCVD of 1 um SiO2 for the spot-size-converter.

11) dicing back side of wafer into 3mm x 5 mm devices

12) cleaving

13) glue to the holder and measuring

Modulated -exposure method for writing EB pattern

EB exposure of waveguide.


Cross-section of developed EB resist.

Different shape of EB resist, which can be achieved by modulated -exposure method by optimizing the gap width and border exposure.
EB exposure of nano contact

The dose for main-body exposure (yellow) should be minimum-possible. The dose for border region(red), width of border region and gap should be optimized to achieve form of EF resist of square shape

a) not good; b) optimum for waveguides c) optimum for nano-magnets, waveguides and lift-off


details for Modulated -exposure method is here

j01 files for JEOL EB writer

EOS mode 8;

top number/10 is size, which needs to input during registration of j01 files

alignment marks (Cr(5 nm)/Au(70 nm)/Cr(5 nm)) should be made using reticle 10

Si nanowire waguides (to download)



jdf files for JEOL EB writer

wavegaide plasmon




ICP -RIE etching of Si nanowaveguides

It consists of 3 Processes, which are done automatically within one run

Process 1 (etching of SiO2 mask)

91(SiO2 start)+82(SiO2 wire)+9 (waiting 30 ")

91 (start plasma for SiO2 etching)
8.5 Pa 200W/0W O2=1sccm CHF3=10sccm 20"
82 (main etching)
1 Pa 200/100 W O2=0.5sccm CHF3=5.0 sccm 40"

Process 2 (etching of Si nano waveguides)

2(SF6 start)+ 3 (SF6 main)+ 9(waiting)

2 (start of plasma)
7 Pa 150/0 W O2=1sccm CHF3=9.0 sccm SF6=1.0 sccm 20"
3 (main etching)
1.5 Pa 65/160 W O2=4sccm CHF3=0.5 sccm SF6=5 sccm 2'25"

I optimize the etching time of the last step about once per half year. Along SOI samples I do the same technology

Process 3 (etching out of EB resist)

Also, this step removes the adhision layer between Si and SiO2 box, which makes for further fabriction steps (in my case it is following steps for fabrication of plasmon waveguides)

98 (O2 etch start)+ 99(O2 etch)

98 (start of plasma)
4 Pa 200/150 W O2=7sccm 5"
99 (main etching)
1 Pa 65/150 W O2=5sccm 1'30"

Wet etching


Q. Why do you use 400 pA beam current?

Q. How long is EB exposure time?

~ 1 hour for Si waaveguides, ~ 10 min for plasmons

























Matlab files to generate, to monitor, to modify .jdf and j01 files






I truly appreciate your comments, feedbacks and questions

I will try to answer your questions as soon as possible


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