Abstract:

All-metal transistor, which does not contain any semiconductor material, may provide benefits of a smaller power consumption, a smaller operational voltage and further size downscaling. Such a transistor is well fitted for the 3D integration. With the availability of such a transistor, the electronic devices may become smaller and more functional.

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Patent: "All-metal transistor and its operational method" , “全金属型トランジスタとその方法” V. Zayets,T. Nozaki, A.Fukushima, S. Yuasa, Patent application 2017-226503, H29/06/06 ( figures; in Japanese; in English)

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What is merits to avoid a semiconductor for fabrication of a transistor or an electrical switch?

Main merit: fit for dense 3D integration

1 Merit of avoiding a semiconductor.

Crystal periodicity is responsible for the existing of a band gap in a semiconductor. A high crystal quality is critical for a semiconductor-based transistor. It is hard to keep the high crystal quality for the 3D integration. In contrast, the proposed transistor can be made from polycrystalline or amorphous materials, quality of which can be sustained over many over-growth processes.

2)  Size downscaling
Currently, Si-made MOSFET transistors are hitting their downscale limit. In contrast, the downscaling ability of the proposed transistor is limited only by the minimum size of the magnetic domain, which could be a couple of nanometers long or shorter. Additionally, the On/Off ratio of the proposed transistor is larger when the size of electrodes and therefore the size of magnetic domains is smaller (See below). As result, the downscaling even improves the performance of the transistor. Therefore, the proposed transistor is well-fitted for a dense 3D integration

3) Merits of a lower operation voltage, a smaller power consumption and the ability to withstand a high current.
A semiconductor-based transistor may operate at a voltage comparable to the band gap of the semiconductor. For example, the band gap of Si is 1.1 eV and the operation voltage of a Si-made transistor is about 1 V. The relatively high operational voltage limits the ability for the reduction of the power consumption for a semiconductor transistor. The proposed transistor has no such limitations.

 

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Why an all-metal transistor may be better than a semiconductor transistor:

1) It can be made only from metal and dielectric material without usage of a semiconductor.

A non-expensive fabrication technique like a sputtering and lift-off can be used. The expensive technique, which is used for fabrication of semiconductors(for example epitaxial growth), can be avoided.

 

2) It can withstand a high current and a high temperature

Electrical constants of a metal only weakly depend on temperature. In contrast, the electrical constants of a semiconductor are substantially varying with a change of temperature. The resistance of a metal is substantially smaller than the resistance of a semiconductor. As result, the metal can withstand a substantially larger current.

 

3) Scaling

(a) in contrast to the MOSFET transistor, the contact resistance does not limit the scaling of the all-metal transistor.

(b) The size of the transistor can be reduced by using the X-ray interferometry for the transistor fabrication instead of the use of the conventional lithography. It is possible because of a simple periodical structure of the all-metal transistor

 

3) Higher speed

The operational speed of MOSFET transistor is limited by the conductivity (the mobility) of Si and it is difficult to improve it. The conductivity of a metal is significantly larger; therefore the all-metal transistor may operate at a faster speed.

 

4) the usage of polycrystalline or amorphous materials

Only single-crystal Si can be used for MOSFET transistor in order to have required mobility. The all-metal transistor can be made from only polycrystalline or amorphous materials. Therefore, expensive growth and fabrication equipment, which are used to grow and to protect a single-crystal material, are not required for the all-metal transistor.

 

4) 3D integration

For the 3D-integration, a new layer of transistors should be fabricated on top of already-fabricated layer. The quality of the transistors should not degrade as a number of layers of transistors increases. It is nearly impossible to keep high-quality of MOSFET transistors fabricated on top of already-fabricated transistor layer. In MOSFET transistor, both the single-crystal and polycrystalline materials are used. It is impossible to grow a single-crystal material on top of a polycrystalline material.  Only polycrystalline or amorphous materials are in the all-metal transistor. Therefore, the quality of transistors can be kept the same for any number of layers for the 3D integration.

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Design of proposed all-metal transistor

 

Design 1. Ferromagnetic metal with in-plane equilibrium magnetization

gate voltage: DC or pulse

 

The magnetization direction under the gate is changed by the VCMA effect.

 

 

 

 

 

Design 2. Ferromagnetic metal with perpendicular -to -plane equilibrium magnetization

 

gate voltage: pulse only

 

 

 

 

 

 

 

 

 

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High MR in FeBTb nanowire with periodically modulated PMA

 

 

Pt induces perpendicular magnetic anisotropy (PMA) in FeBTb.

Additionally, there is a volume-type PMA in FeBTb. As a result, a thicker FeBTb nanowire has a larger PMA than a thinner nanowire.

Under Pt gate the PMA is larger than in the gap between electrodes, because interface PMA at Pt/FeBTb interface and because in this region the FeBTb is thicker.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Measuring magnetization under gate electrode and in gap between electrodes

 

In order to optimize the transistor, it is important to measure the magnetization independently and simultaneously in regions under the electrode and in gap between electrodes. It clarifies whether

(1) magnetization is magnetically decoupled in these regions

(2) magnetization direction in each region

 

The size of tip of Hall bar should be sufficiently narrow! Now I am able to make the tip as narrow as 40-50 nm.

The alignment of tip should be very precise! Now I am able to make the alignment between Hall probe and the periodical electrode with 10 nm precision.

 

 

 

 

 

 

 

 

 

 

 

 

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Coupling & decoupling of magnetization in regions under gate and in gap between gates

The exchange interaction between regions under gate and in gap between gates forces forces

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Gate with periodical change of polarity

In this structure, a gate voltage of opposite polarities is applied to neighbor gate electrode. As a result, under one gate electrode the PMA of the nanowire increases and under neighbor electrode the PMA decreases. That enhances the formation the gate-voltage-induced domain structure in the nanowire.

 

 

 

 

 

 

 

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Pinning of domain wall & Pinning of magnetization in gap between gate electrodes

The pinning of domain wall and pinning of magnetization in gap between gate electrodes are critically important for the operation of the transistor.

A different thickness of nanowire is used to pin firmly the domain at the boundary between the gate electrode and the gap.

The material with a large interfacial PMA is deposited in the gap between gate electrode in order to pin the magnetization in this region

 

 

 

 

 

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Effect of accumulated magneto-resistance

 

In fact, the magneto-resistance (MR) is not accumulated effect. The total magneto-resistance of two or more MR elements, which are connected either parallel or in series, is smaller or equal to the magneto-resistance of each MR element.

In contrast, in a nanowire with magnetic domains the magneto-resistance may be accumulated

Example 1: Two MR elements are connected in series

In this case total resistance can be calculated as

where are resistance of 1st and 2d elements of their two electrodes are parallel. are resistance of 1st and 2d elements of their two electrodes are anti parallel.

The total magneto-resistance can be calculated as

in the case when two MR elements have an equal magneto-resistance , the total MR is the same as MR of each element

Example 2: Two MR elements are connected in parallel

In this case total resistance can be calculated as

in the case when MR and resistance are equal

The total resistance can be calculated from Eq.(1.4) as

From Eq. (1.6), the total MR is calculated as

the total MR is the same as MR of each element

 

Accumulation of magneto-resistance in a nanowire with magnetic domains

 

 

The magneto-resistance of a ferromagnetic nanowire with domain walls is calculated as

where R_bulk is the bulk resistance of the nanowire without any domains, R_wall is the resistance of one domain wall and n is number of domain walls.

From Eq(2.1), is MR is calculated as

 

The magneto-resistance (MR)increases when number of domain walls n increases and domain size decreases!!

 

 

 

 

 

 

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How large is the resistance R_wall of one domain wall?

The change of resistance on nanowire, which is made of Fe or Co, is about 0.1-0.01% (70 K) ( Kent et al, JCMCP (2001)) . Usually, it is about the same magnitude as the resistivity change due to the Anisotropic magnetoresistance (AMR). I have never observed the domain wall resistance in Fe, FeB, Co in my experiments at room temperature. Even though I have fabricated a nanowire made of these materials with 50 nm long domains, which was checked by Hall measurements (See here). In contrast, a nanowire made of a compensated ferromagnet (like FeBTb) always shows a substantial domain wall resistance and a substantial AMR. I am not sure weather the domain wall resistance and the AMR are related.

The resistance of one domain was measured in 60-nm-wide FePd nanowire at 17 K. It was about 0.01 Ohm, when total resistance of nanowire was 3 Ohm (Danneau et al, PRL 2002)

 

 

How to increase the domain-wall-induces magneto-resistance?

method 1: Reduce size of a domain

The smaller domain size , the larger MR ! See fig. above. The periodically-modulated PMA is the method to obtain the shortest domain.

method 2: Make a shorter domain wall

The magnetization direction is opposite for neighbor domains. The spin direction of spin-polarized conduction electrons is along the magnetization in the bulk of the domain. However, in the region of the domain wall the spin-polarization becomes zero (See here). The magneto-resistance may occurs when electron current is passing through the regions of different spin polarization of the conduction electrons. The steeper the change of spin polarization is, the larger the MR is. Therefore, the domain structure with the shortest domain wall is required in order to obtain a substantial MR.

Example: (1) in Fe:MgO:Fe MTJ device, the spin polarization of the conduction electrons changes sharply from one Fe electrode to another Fe electrode. As a result, the MR is very high ~100 %; (2) in Co:Cu:Co p-GMR device , the spin polarization changes very gradually from one Co electrode to another Co electrode. As a result, the MR is moderate ~0.1 %; It should be noted that other material parameters influence the MR, but tendency is clear.

method 3. Use a compensated ferromagnetic material or an antiferromagnetic material as a material of nanowire

Up to now (Aug.2018) I have never detected any domain wall resistance in a nanowire made of FeB or Co or Fe, which were measured at room temperature. However, I often detect the domain wall resistance in the compensated ferromagnetic FeBTb.

method 4 Use a material with a low conductivity. Use a "bad" conductor

All spin-dependent features more manifest themselves in a metal with a lower conductivity (in a "bad" conductor). The reason for this is that the nature of electrical current is very different from that in a "good" conductor. (See here). The magneto-resistance only may occur in the "bad" conductor, but it can not be any magneto-resistance in the "good" conductor (See here).

 

 

Why the most of reports on the resistance of a domain wall is done at low temperature?

There are two reasons for that:

reason 1: The spin polarization of the conduction electrons becomes larger due reduction of the spin relaxation time (See here).

reason 2: The gradient of the spin polarization in the region of the domain wall becomes sharper.

 

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Main Challenges

Main challenge is to obtain a sufficient domain wall resistance.

It can be only achieved in a metal with a high resistivity. There is a fundamental reason for that (See here)

 

 

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Convolutional Neural Network

The proposed design may be used as a memory element of a Neural Network.

Many neuromorphic specific circuits can be represented as neural gates performing the operation of a “dot product” of vectors of analog inputs and stored weights (synapses), followed by a non-linear threshold function (a neuron).

A logic element has only two states: 0 and 1. For neuron computing, a memory element with a larger number of states is required. In the proposed design, the resistance of the device can be increased by given amount when the gate voltage is applied only to some (not to all) electrodes and only some of domains are reversed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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I am strongly against a fake and "highlight" research