AIST > RCIS > Members > Akashi Satoh

Akashi Satoh, Ph. D.

Team Leader of Research Team for Hardware Security,
Research Center for Information Security (RCIS),
National Institute of Advanced Industrial Science and Technology (AIST)

E-mail: akashi.satoh @ aist.go.jp

Research Topics

I have been involved in the research and development of high-performance VLSI circuits since 1989. My current research interests include hardware algorithms and architectures for information security. The main focus of our research team is the physical analysis attack of cryptographic software and hardware modules. We developed SASEBO (Side-channel Attack Standard Evaluation BOard) in order to establish a standard experimental environment for side-channel attacks and to develop standard security evaluation schemes for cryptographic modules.

Curriculum Vitae

Education

March 1999, Ph.D. (Engineering), Waseda University

March 1989: M.E., Graduate School of Science and Engineering, Waseda University
March 1987: B.E., School of Science and Engineering, Waseda University

Work Experience

April 2007 - present: RCIS, AIST
April 1989 - March 2007: Tokyo Research Laboratory, IBM Japan

Worlds' fastest 4M-bit DRAM (1989-91)
Low-power DRAM project at Burlington Laboratory (1991)
High-speed Reed-Solomon error correction circuit for flash memory card (1991-92)
High-speed ALDC data compression hardware for tape drive at Burlington Laboratory (1992-93)
DRAM-Logic mixed LSI technology development at Watson Research Center (1994-96)
Worlds' fastest and most compact RSA LSI (1996-97)
PKI support LSI for Sony fingerprint ID module PUPPY (1998)
SSL accelerator PCI board (1999)
MARS hardware development for the AES project (1999-2000)
Security hardware prototype board for video game (2000)
DES accelerator on PowerPC 405LP (2001)
Encrypted HDD with AES circuit (2002)
Cryptographic and data compression hardware/software for multi-functional printer (2003)
Digital image protection for multi-functional printer (2004)
High-speed AES circuit for the Z9 processor (2005)
Encrypted tape drive (2005-06)

Part-time Lecturer: Tokyo Institute of Technology (2006). Tamagawa University (2001)

Professional Activities

Editorial Board: IPSJ magazine, 1999-2001.
Member: CRYPTREC, Japan, 2002-
Permanent Paper Referee: IEICE Transactions, 2002-
Program Committee: ISC 2003, Bristol, UK, Oct. 1-3, 2003.
Program Committee: ACISP2005, Brisbane, Australia, Oct. 7-8, 2005.
Local Arrangement Committee: CHES 2006, Yokohama, Japan, Oct. 10-13, 2006.
Progmram Committee: CHES 2007, Vienna, Austria, Sep. 10-13, 2007.
Program Committee: CHES 2008, Washington D.C., USA, Aug. 10-13, 2008.
Program Committee: ReConfig'08, Cancun, Mexico, Dec. 3-5, 2008.
Session Orginzer: IEEE ISCAS 2009 Security Systems on Silicon: Wireless and Mobile Networks, Taipei, Taiwan, May 24-27, 2009.
Program Committee: IWSEC2009, Toyama, Japan, Oct. 28-30, 2009.
Program Committee: ReConfig'09, Cancun, Mexico, Dec. 9-11, 2009.
Program Committee: COSADE 2010, Darmstadt, Germany, Feb. 4-5, 2010.
Asian Liaison: HOST 2010, Anaheim, USA, Jun. 13-14, 2010.
Program Committee: CHES 2010, Santa Babara, USA, Aug. 19-20, 2010.
Program Committee: FDTC 2010, Santa Babara, USA, Aug. 21, 2010.
Program Committee: ReConfig'10, Cancun, Mexico, Dec. 13-15, 2010.
Program Committee: COSADE 2012, Darmstadt, Germany, Feb. 24-25, 2011.
Asian Liaison: HOST 2011, San Diego, USA, Jun. 5-6, 2011.
Program Committee: DSD 2011, Oulu, Finland, Aug. 31 - Sep. 2, 2011.
Programl Chair: NIAT 2011, Nara, Japan, Sep. 26-27, 2011.
General Chair: CHES 2011, Nara, Japan, Sep. 28 - Oct. 1, 2011.
Program Committee: ReConfig 2011, Cancun, Mexico, Nov. 30 - Dec. 2, 2011.
Program Committee: COSADE 2012, Darmstadt, Germany, May 3-4, 2012.
Steering Committee: CHES 2012, Leuven, Belgium, Sep. 9-12, 2012.